Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Input/Output Delay Switching Characteristics
Table 53: Input/Output Delay Switching Characteristics
Symbol
Description
-3
Speed Grade
-2 -1
-1L
Units
IDELAYCTRL
T DLYCCO_RDY
Reset to Ready for IDELAYCTRL
3.00
3.00
3.00
3.25
μs
F IDELAYCTRL_REF
REFCLK frequency =
REFCLK frequency =
200.0 (1)
300.0 (1)
200
300
200
300
200
200
MHz
MHz
IDELAYCTRL_REF_PRECISION
T IDELAYCTRL_RPW
REFCLK precision
Minimum Reset pulse width
±10
50.00
±10
50.00
±10
50.00
±10
52.50
MHz
ns
IODELAY
T IDELAYRESOLUTION
IODELAY Chain Delay Resolution
1/(32 x 2 x F REF )
ps
Pattern dependent period jitter in delay
0
0
0
0
ps
chain for clock pattern. (2)
per tap
Pattern dependent period jitter in delay
±5
±5
±5
±5
ps
T IDELAYPAT_JIT
chain for random data pattern
(PRBS 23). (3)
per tap
Pattern dependent period jitter in delay
±9
±9
±9
±9
ps
chain for random data pattern
(PRBS 23). (4)
per tap
T IODELAY_CLK_MAX
T IODCCK_CE / T IODCKC_CE
T IODCK_INC / T IODCKC_INC
T IODCCK_RST / T IODCKC_RST
T IODDO_T
T IODDO_IDATAIN
T IODDO_ODATAIN
Maximum frequency of CLK input to
IODELAY
CE pin Setup/Hold with respect to CK
INC pin Setup/Hold with respect to CK
RST pin Setup/Hold with respect to CK
TSCONTROL delay to MUXE/MUXF
switching and through IODELAY
Propagation delay through IODELAY
Propagation delay through IODELAY
500.00
0.45/
–0.09
0.23/
–0.02
0.57/
–0.08
420.00
0.53/
–0.09
0.27/
–0.01
0.62/
–0.08
300.00
0.65/
–0.09
0.31/
0.00
0.69/
–0.08
300.00
0.84/
–0.14
0.27/
–0.04
0.74/
–0.13
MHz
ns
ns
ns
ps
ps
ps
Notes:
1.
2.
3.
4.
5.
Average Tap Delay at 200 MHz = 78 ps, at 300 MHz = 52 ps.
When HIGH_PERFORMANCE mode is set to TRUE or FALSE.
When HIGH_PERFORMANCE mode is set to TRUE
When HIGH_PERFORMANCE mode is set to FALSE.
Delay depends on IODELAY tap setting. See TRACE report for actual values.
CLB Switching Characteristics
Table 54: CLB Switching Characteristics
Symbol
Description
-3
Speed Grade
-2 -1
-1L
Units
Combinatorial Delays
T ILO
An – Dn LUT address to A
An – Dn LUT address to AMUX/CMUX
An – Dn LUT address to BMUX_A
0.06
0.18
0.28
0.07
0.20
0.31
0.07
0.22
0.36
0.09
0.25
0.40
ns, Max
ns, Max
ns, Max
DS152 (v3.6) March 18, 2014
Product Specification
41
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